SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.33 IDE0 Task File Timing + Configuration + Status
Address Offset: A0H
Access Type: Read/Write
Reset Value: 0x6515_0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
Reserved
This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
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Bit [31:28]: Addr Setup Count (R/W) – IDE0 Address Setup Time Count. This bit field is used for adjusting the
address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming
the timing register.
Bit [27:22]: Active Count (R/W) – IDE0 DIOR_N and DIOW_N Active Time Count. This bit field is used for
adjusting the active time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming this
timing register.
Bit [21:16]: Recovery Count (R/W) – IDE0 DIOR_N and DIOW_N Recovery Time Count. This bit field is used
for adjusting the recovery time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on
programming this timing register.
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Bit [15]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [14] : Watchdog Int Ena ( R/W ) – IDE0 Watchdog Interrupt Enable. This bit is set to enable Interrupt when
Watchdog timer expired.
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Bit [13]: Watchdog Ena (R/W) – IDE0 Watchdog Timer Enable. This bit is set to enable the watchdog timer for
IDE0. This bit is cleared to disable the watchdog timer.
Bit [12]: Watchdog Timeout (R/W1C) – IDE0 Watchdog Timer Timeout. This bit set indicates that the watchdog
timer for IDE0 timed out. When enabled, and IORDY monitoring bit is also enabled, during IDE0 PIO opeartion,
the watchdog counter starts counting when IORDY signal is deasserted. If after 256 PCI clocks cycles, the
IORDY signal is still deasserted, the Watchdog Timer is expires, and this bit is set and the SiI 0680A continue its
operation and stop monitoring IORDY signal. Software writes one to clear this bit. Once this bit is cleared, the SiI
0680A starts monitoring IORDY on channel 0 again.
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Bit [11]: Interrupt Status (R) – IDE0 Interrupt Status. This bit set indicates that an interrupt is pending on IDE0.
This bit provides real-time status of the IDE0 interrupt pin.
Bit [10]: Virtual DMA Int (R) – IDE0 Virtual DMA Completion Interrupt. This bit set indicates that the Virtual DMA
data transfer has completed. This bit is cleared when bit[0] PBM enable in PCI Bus Master – IDE0 is cleared .
Bit [09]: IORDY Monitoring (R/W) – IDE0 IORDY Monitoring. When this bit is set, IORDY line is monitored for
Task File accesses on channel 0.
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Bit [08:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]: Channel Tri-State (R/W) – IDE0 Channel Tri-State. This bit is set to tri-state the IDE Channel #0 bus.
This bit is cleared for normal operations.
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Bit [02]: Channel Rst (R/W) – IDE0 Channel Reset. When this bit is set, IDE Channel #0 RST signal is
asserted.
Bit [01]: Buffered Cmd (R) – IDE0 Buffered Command Active. This bit set indicates that a Buffered Command is
currently active. This bit is set when the first command byte is written to the command buffer. This bit is cleared
when all of the task file bytes, including the command byte, have been written to the device.
Bit [00]: Cable 80 (R) – IDE0 Cable 80 Detection. This bit provides real-time status of the inverted version of
the IDE0_CBLID_N pin. When set, it indicates that 80 pin cable is detected.
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© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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