SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Table of Tables
Table 2-1: Absolute Maximum Ratings......................................................................................................................................14
Table 2-2: DC Specifications......................................................................................................................................................14
Table 2-3: PCI 33 MHz Timing Specifications............................................................................................................................15
Table 2-4: ATA /ATAPI-6 Slew Rate Specifications ...................................................................................................................15
Table 2-5: ATA/ATAPI-6 DC Specifications ...............................................................................................................................15
Table 3-1: SiI 0680A Pin Listing .................................................................................................................................................17
Table 3-2: ATA Configuration....................................................................................................................................................30
Table 3-3: Base Address 5 Configuration..................................................................................................................................31
Table 5-1: PCI Bus Signals Group .............................................................................................................................................35
Table 5-2: IDE Channel #0 Signals Group .................................................................................................................................35
Table 5-3: IDE Channel #1 Signals Group .................................................................................................................................35
Table 5-4: SiI 0680A FLASH Memory Signals Group – Shared Signals.....................................................................................36
Table 5-5: SiI 0680A EEPROM Memory Signals Group – Shared Signals.................................................................................36
Table 5-6: SiI 0680A Test Signals Group...................................................................................................................................36
Table 8-1: Auto-Initialization from Flash Timing .........................................................................................................................43
Table 8-2: FLASH Data Description ...........................................................................................................................................44
Table 8-3: Auto-Initialization from EEPROM Timing..................................................................................................................45
Table 8-4: Auto-Initialization from EEPROM Timing Symbols....................................................................................................45
Table 8-5: EEPROM Data Description .......................................................................................................................................45
Table 9-1: SiI 0680A PCI Configuration Space ..........................................................................................................................46
Table 9-2: SiI 0680A Internal Register Space – Base Address 0 ..............................................................................................63
Table 9-3: SiI 0680A Internal Register Space – Base Address 1 ..............................................................................................64
Table 9-4: SiI 0680A Internal Register Space – Base Address 2 ..............................................................................................65
Table 9-5: SiI 0680A Internal Register Space – Base Address 3 ..............................................................................................66
Table 9-6: SiI 0680A Internal Register Space – Base Address 4 ..............................................................................................67
Table 9-7: SiI 0680A Internal Register Space – Base Address 5 ...............................................................................................71
Table 9-8: Software Data Byte, Base Address 5, Offset 00H .....................................................................................................72
Table 9-9: Software Data Byte, Base Address 5, Offset 10H .....................................................................................................74
Table 9-10: IDE0 Test Register Selections ...............................................................................................................................93
Table 9-11: IDE1 Test Register Selections ..............................................................................................................................101
Table 10-1: Test Mode Register Selections .............................................................................................................................104
Table 10-2: SiI 0680A NAND Tree Order.................................................................................................................................105
Table 10-2, SiI 0680A NAND Tree Order (continued) ..............................................................................................................106
Table 11-1, Physical Region Descriptor (PRD) Format ............................................................................................................117
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
7
SILICONIMAGE [ Silicon image ]
