SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
11.9.1 Using Virtual DMA with Non-DMA Capable Devices......................................................................... 114
11.9.2 Using Virtual DMA with DMA Capable Devices................................................................................. 116
11.10 Second PCI Bus Master Registers Usage........................................................................................... 116
12. FLASH and EEPROM Programming Sequences........................................................................118
12.1 FLASH Memory Access........................................................................................................................... 118
12.1.1 PCI Direct Access .................................................................................................................................................118
12.2.2 Register Access ....................................................................................................................................................118
12.2 EEPROM Memory Access....................................................................................................................... 119
13. SiI 0680A Timing Registers..........................................................................................................120
13.1 Timing Register Definition...................................................................................................................... 120
13.2 Timing Registers Programming Suggestion ........................................................................................ 121
13.2.1 TF Timing Register Programming in Number of 33 MHz PCI clock.......................................................................121
13.2.2 PIO Timing Register Programming in Number of 33 MHz PCI clock.....................................................................121
13.2.3 DMA Timing Register Programming in Number of 33 MHz PCI clock ...................................................................121
13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock...............................................................121
13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock...............................................................121
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
6
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