SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
14. Errata
The 680A returns Target Abort when CBE#[3:0] = 1111
When an access is made to the 680A memory region with Data Byte Enable = 0FH (no data to be transferred) and the
address is within the 680A Delay-Transaction Region, instead of terminating the transaction normally, terminates
the transaction with Target Abort. This does not comply with the PCI specification and may result in system errors in some
systems.
This may happen when the 680A is on a 64-bit PCI bus and the host issues a 64-bit transaction with only low or high Dword
bytes enabled. Since 680A only supports 32-bit transactions, the host may break the 64-bit transaction into two 32-bit
transactions in which, one of the transactions is a dummy transaction with all Byte Enables set to 1111.
The Delay-Transaction Region on the 680A includes: the FIFO region (BA5 + (60h-7Fh)); the IDE0 Task File Region (BA5 +
(80h-8Fh)); and the IDE1 Task File Region (BA5 + (C0h-CFh)).
Impact: May result in system errors in some systems.
Workaround: At present this has only been observed in an environment in which conditions have been forced with a PCI
bridge device. No tested motherboards have experienced problems.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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