SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
13.2 Timing Registers Programming Suggestion
13.2.1 TF Timing Register Programming in Number of 33 MHz PCI clock
TF 0
3
10
TF 1
2
10
TF 2
1
10
TF 3
1
3
TF 4
1
3
Address Setup
Active Count
10
328Ah
3
1
3
1
Recovery Count
TF Timing Register
2283h
1281h
10C3h
10C1h
13.2.2 PIO Timing Register Programming in Number of 33 MHz PCI clock
PIO 0
3
10
PIO 1
2
10
PIO 2
1
4
PIO 3
1
3
PIO 4
1
3
Address Setup
Active Count
10
328Ah
3
4
3
1
Recovery Count
PIO Timing Register
2283h
1104h
10C3h
10C1h
13.2.3 DMA Timing Register Programming in Number of 33 MHz PCI clock
MDMA 0
MDMA 1
MDMA 2
2
8
1
3
1
3
Address Setup
Active Count
8
2
1
Recovery Count
PIO Timing Register
2208h
10C2h
10C1h
13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock
UDMA 0
UDMA 1
UDMA 2
UDMA 3
UDMA 4
UDMA 5
11
7
5
4
2
1
Cycle
13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock
UDMA 0
UDMA 1
UDMA 2
UDMA 3
UDMA 4
UDMA 5
UDMA 6
15
11
7
5
3
2
1
Cycle
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
121
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