SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
If the ATA/ATAPI device has interrupted,
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device
interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – IDEx register to clear the DMA Complete bit (NOTE: The
DMA Complete bit acts as a latched copy of the ATA interrupt line when the channel is not
performing a DMA operation).
If the ATA/ATAPI device is not reporting an error, and DRQ is asserted (bit 27 of IDEx Task File
Register 1), then the device is interrupting to transfer data to the device. To transfer the data, the
DMA registers are setup to only perform that part of the data transfer expected for this interrupt.
The DMA is setup similarly to the way it is when performing a normal write DMA command, but with
one additional step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte
Count register must be written with the 32-bit count of the number of bytes to be transferred for this
interrupt.
Repeat the above steps starting at “Wait for PCI interrupt” until all data for the write command has been
transferred or an error has been detected.
11.9.2 Using Virtual DMA with DMA Capable Devices
Even though a device may be DMA capable, there are ATA/ATAPI commands that require that a PIO mode be used to
transfer data. For these commands, virtual DMA can be used to perform the data transfer. Using virtual DMA with an
ATA/ATAPI device that has already been configured to use DMA for normal read/write operation is performed very much like
the sequence described above for PIO mode only devices, but with the following additional considerations:
•
The Data Transfer Mode – IDEx register associated with the ATA/ATAPI device needs to be
programmed for a PIO type transfer mode before DMA operation is enabled, and must be re-
programmed with the DMA/UDMA transfer type used during normal DMA operation once the virtual
DMA operation is complete.
•
A PIO mode compatible with the device should be programmed into the appropriate IDEx – PIO Timing
register. This register does not have to be written for every command that uses virtual DMA, instead it
should be written as part of the controller initialization sequence.
11.10 Second PCI Bus Master Registers Usage
In order to provide backward compatibility with existing drivers, the Physical Region Descriptor (PRD) tables used by the 680A
controller when performing DMA transfers suffer the following limitations; a PRD table entry cannot represent a memory area
greater than 64k, nor can a PRD table entry represent a memory area that spans a 64k address boundary. Whenever DMA is
initiated via the PCI Bus Master – IDEx registers, the foregoing limitations are enforced by the 680A controller.
A feature known as Large Block Transfer has been added to the SiI 0680A controller to allow new drivers to get around the 64k
size and address limits of PRD table entries expected by existing drivers. Large Block Transfer simplifies the creation of PRD
tables by reducing the number of table entries that need to be created and eliminating the need to make sure a memory region
does not cross a 64k boundary. Large Block Transfer mode is enabled whenever DMA is initiated by writing to the PCI Bus
Master 2 – IDEx registers (base address 5, offset 10H or 18H). When performing DMA in Large Block Transfer mode, the 680A
controller interprets the fields of a PRD table entry differently. In all other respects, DMA interrupt generation, DMA status bit
interpretation, etc…, Large Block Transfer mode behaves identically to a non-Large Block Transfer mode DMA operation. The
following table describes the format of a PRD table entry:
Bits 31:0
32-bit starting address of the memory region.
Bits 47:32 When not operating in Large Block Transfer mode, this field specifies the size
of the memory region. If the size of the memory region is greater than 64k, or
crosses a 64k address boundary, then two or more PRD table entries will need
to be created to describe it.
If operating in Large Block Transfer mode, this field contains the least
significant 16-bits of the size of the memory region.
Bits 62:48 If not operating in Large Block Transfer mode, this field is unused.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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