SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
13. SiI 0680A Timing Registers
13.1 Timing Register Definition
RECOVERY COUNT TIMING
Bits [21:16] IDE0 Task File Timing + Configuration + Status
Bits [05:00] IDE0 PIO Timing
Bits [21:06] IDE0 PIO Timing
Bits [05:00] IDE1 PIO Timing
Bits [21:06] IDE1 PIO Timing
ACTIVE COUNT TIMING
Bits [27:22] IDE0 Task File Timing + Configuration + Status
Bits [11:06] IDE0 PIO Timing
Bits [27:22] IDE0 PIO Timing
Bits [11:06] IDE1 PIO Timing
Bits [27:22] IDE1 PIO Timing
Value
Active Time in PCI Clock
00h
01h
02h
03h
...
1
1
2
3
3Fh
63
ADDRESS SETUP COUNT TIMING
Bits [31:28] IDE0 Task File Timing + Configuration + Status
Bits [15:12] IDE0 PIO Timing
Bits [31:28] IDE0 PIO Timing
Bits [15:12] IDE1 PIO Timing
Bits [31:28] IDE1 PIO Timing
Value
Active Time in PCI Clock
0h
1h
2h
3h
1
1
2
3
UDMA Cycle Time Count Timing
Value
Cycle Time in IDE Clock
00h
01h
02h
03h
...
2
2
3
4
3Fh
64
In the UDMA timing register. the number of clocks is always 1 greater than the value loaded for the cycle time
count. The only exception is that value "0" requires two cycles.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
120
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