SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the
steps below (assuming that the virtual DMA operation completed successfully).
If the ATA/ATAPI device has interrupted,
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device
interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – IDEx register to clear the DMA Complete bit (NOTE: The
DMA Complete bit acts as a latched copy of the ATA interrupt line when the channel is not
performing a DMA operation).
If the ATA/ATAPI device is not reporting an error, and DRQ is asserted (bit 27 of IDEx Task File
Register 1), then the device is interrupting to transfer data to the host. To transfer the data, the
DMA registers are setup to only perform that part of the data transfer expected for this interrupt.
The DMA is setup similarly to the way it is when performing a normal read DMA command, but with
one additional step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte
Count register must be written with the 32-bit count of the number of bytes to be transferred for this
interrupt.
Repeat the above steps until all data for the read command has been transferred or an error has been
detected.
Write Operation
Poll the IDEx Task File Register 1 bits [31:24] until either bit 27 (DRQ) is set indicating the device is ready for
write data transfer, or bit 24 (ERR) is set indicating the device has detected an error with the write command.
If no error, and DRQ is asserted (bit 27 of IDEx Task File Register 1), then the device is waiting for write data
transfer. To transfer the data, the DMA registers are setup to only perform that part of the data transfer
expected at this time. For example, a Write Sectors command would expect to transfer 1 sector (512 bytes),
while a Write Multiple command would expect to transfer the lesser of the number of sectors set by the Set
Multiple Mode command or the total number of sectors specified by the Write Multiple command. The DMA
is setup similarly to the way it is when performing a normal write DMA command, but with one additional
step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte Count register must be
written with the 32-bit count of the number of bytes to be transferred.
Wait for a PCI interrupt.
Read the DMA status bits [18:16] of the PCI Bus Master – IDEx register, and check that bit 18 is set to make
sure the interrupt was generated by the expected channel.
If expected channel interrupted, read bits [11:10] of the channel’s IDEx Task File Timing + Configuration +
Status register to determine the cause of the interrupt. Bit 11 is set if the ATA/ATAPI device has an interrupt
pending, bit 10 is set if a virtual DMA operation completed.
If a virtual DMA operation completed,
Write 00H to bits [7:0] of the PCI Bus Master – IDEx register to disable DMA operation.
Write 1 to bits [18:17] of the PCI Bus Master –IDEx register to reset the DMA status and virtual
DMA interrupt bits, and PCI interrupt.
Check the previously read DMA status bits to ensure the DMA completed successfully. See section
11.8 for more information about interpreting the DMA status bits.
Because ATA/ATAPI commands that transfer data using PIO can generate several interrupts
during the data transfer phase of the command, a race condition is created between the interrupt
indicating the completion of a virtual DMA operation, and the interrupt from the ATA/ATAPI device
indicating it is ready to perform the next part of the data transfer. To prevent missing an
ATA/ATAPI device interrupt due to this race condition, it is necessary to re-read the channel’s IDEx
Task File Timing + Configuration + Status register after disabling DMA operation and examining bit
11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the
steps below (assuming that the virtual DMA operation completed successfully).
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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