SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Make sure PCI bus master operation of the SiI 0680A is stopped by clearing bit 0 of the PCI Bus Master –
IDEx register.
Note: The task file registers are not accessible as long as bit 0 is set. Clearing bit 0 causes bit 16 to be
cleared as well.
Read the device status at bits [13:24] in the IDEx Task File Register 1 register to clear the device interrupt
and determine if there was error.
Write ‘1’ to bit 18 (write-one-to-clear) in the PCI Bus Master – IDEx register to clear the PCI Interrupt.
11.9 IDE Virtual DMA Read/Write Operation
In virtual DMA operation the controller uses a PIO data transfer mode to move data between an ATA/ATAPI device and the
controller, and uses DMA to move that same data between the controller and the host memory. For ATA/ATAPI devices that
cannot operate in a “true” DMA mode, virtual DMA provides two benefits; first, using DMA to move data reduces the demand
on the host CPU, and second, systems that use virtual memory often require that data buffers that will be accessed directly by
low level device drivers be “mapped” into the operating system’s address space, in virtual DMA mode the CPU does not
access the data buffer directly, so the overhead of obtaining the mapping to operating system address space is eliminated.
11.9.1 Using Virtual DMA with Non-DMA Capable Devices
Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized
for PIO mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for PIO mode data
transfer per the instructions in section 11.3, virtual DMA read/write operations may be performed by following the programming
sequence described below.
NOTE: The watchdog timer feature is compatible with virtual DMA operation. See section 11.7 for details about using the
watchdog timer.
Issue a PIO read/write command to the device following steps in section 11.4.
Read Operation
Wait for a PCI interrupt.
Read the DMA status bits [18:16] of the PCI Bus Master – IDEx register, and check that bit 18 is set to make
sure the interrupt was generated by the expected channel.
If expected channel interrupted, read bits [11:10] of the channel’s IDEx Task File Timing + Configuration +
Status register to determine the cause of the interrupt. Bit 11 is set if the ATA/ATAPI device has an interrupt
pending, bit 10 is set if a virtual DMA operation completed.
If a virtual DMA operation completed,
Write 00H to bits [7:0] of the PCI Bus Master – IDEx register to disable DMA operation.
Write 1 to bits [18:17] of the PCI Bus Master –IDEx register to reset the DMA status and virtual
DMA interrupt bits, and the PCI interrupt.
Check the previously read DMA status bits to ensure the DMA completed successfully. See section
11.8 for more information about interpreting the DMA status bits.
Because ATA/ATAPI commands that transfer data using PIO can generate several interrupts
during the data transfer phase of the command, a race condition is created between the interrupt
indicating the completion of a virtual DMA operation, and the interrupt from the ATA/ATAPI device
indicating it is ready to perform the next part of the data transfer. To prevent missing an
ATA/ATAPI device interrupt due to this race condition, it is necessary to re-read the channel’s IDEx
Task File Timing + Configuration + Status register after disabling DMA operation and examining bit
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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