SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
11.7 IDE PIO Mode Read Ahead Operation
Read ahead operation allows the controller to “pre-fetch” data from the IDE bus and store it in the controller’s channel fifo,
where it will later be retrieved by the host. This mode of operation has the potential to speed-up PIO data transfers by not
forcing the host to wait the programmed PIO cycle time for every access to the task file data register. The amount of any
speed increase will depend on the PIO mode in use, the characteristics of the host PCI bus, as well as the speed of the host
processor.
To use the controller’s PIO read ahead capability, make the following changes to the “Read Operation” portion of sections 11.5
and 11.6.
Just prior to retrieving the read data, set the read ahead byte count by programming bits [15:00] in the IDEx
Virtual DMA/PIO Read Ahead Byte Count register with the exact number of bytes to be read for the interrupt.
Instead of reading the IDEx Task File Register 0 register to retrieve the data, read the IDEx Read Ahead
Data register instead.
11.8 IDE MDMA/UDMA Read/Write Operation
Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized
for MDMA/UDMA mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for
MDMA/UDMA mode data transfer per the instructions in section 11.3, DMA read/write operations may be performed by
following the programming sequence described below.
Issue a DMA read/write command to the device following steps in section 11.4.
Program Bus Master Registers
Clear bit 17 in the PCI Bus Master – IDEx register. This bit is set if an error occurred during the previous
DMA access.
Clear bit 18 in the PCI Bus Master – IDEx register. This bit is set if an IDE interrupt occurred during the
previous DMA access.
Create a Physical Region Descriptor (PRD) Table.
A PRD table is an array where each entry describes the location and size of a physical memory buffer that
will be used during the DMA operation. Each PRD table entry is 64-bits in length, formatted as follows; bits
[31:0] contain the 32-bit starting address of the memory buffer, bits [47:32] contain the 16-bit size of the
memory buffer, bits [62:48] are normally unused (see section 11.10 for details of how these bits may be
used), bit 63 flags the end of the PRD table and therefore should only be set in the last entry of the PRD
table. The PRD table itself must be constructed in a memory region that can be directly accessed by the
680A controller. Once the PRD table is built, the controller must be informed of its location. This is
accomplished by writing the 32-bit address of the PRD table to the PRD Table Address – IDEx register.
Enable DMA transfer.
DMA is enabled by writing bits [7:0] of the PCI Bus Master – IDEx register. Bit 3 of this register controls the
direction of the DMA transfer; 1 = write to memory, 0 = read from memory. Setting bit 0 of the register
enables the controller to perform DMA operations.
Note: Task file registers are inaccessible as long as bit 0 is set.
Wait for a PCI interrupt.
When a PCI interrupt occurs, read the PCI Master – IDEx status register and check the DMA status bits. The
possible combinations of the status bits [18:16] are defined below.
000B = If the IDE device does not report an error, then the PRD table specified a size that is smaller
than the IDE transfer size.
001B = DMA transfer in progress.
010B = The controller had a problem transferring data to/from memory.
100B = Normal completion.
101B = If the IDE device does not report an error, then the PRD specified a size that is larger than
the IDE transfer size.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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