SiM3C1xx
Table 3.12. Capacitive Sense
Parameter
Symbol
Conditions
12-bit Mode
13-bit Mode
14-bit Mode
16-bit Mode
Min
—
Typ
25
27
29
33
45
Max
—
Units
µs
Single Conversion Time
(Default Configuration)
t
single
—
—
µs
—
—
µs
—
—
µs
Maximum External Capacitive Load
C
C
Highest Gain Setting
(default)
—
—
pF
L
L
Lowest Gain Setting
—
—
500
50
—
—
pF
Maximum External Series Imped-
ance
Highest Gain Setting
(default)
k
Table 3.13. Current-to-Voltage Converter (IVC)
Parameter
Supply Voltage (VDD)
Symbol
Conditions
Min
2.2
Typ
—
Max
3.6
Units
V
V
DDIVC
Input Pin Voltage
Minimum Input Current (source)
Integral Nonlinearity
Full Scale Output
Slope
V
2.2
—
VDD
—
V
IN
IN
I
100
–0.6
—
—
µA
%
INL
—
0.6
IVC
IVCOUT
V
1.65
1.66
—
V
M
Input Range 1 mA
(INxRANGE = 101)
1.62
1.73
V/mA
IVC
Input Range 2 mA
(INxRANGE = 100)
810
540
400
320
265
—
830
550
415
330
275
—
855
565
425
340
285
500
mV/mA
mV/mA
mV/mA
mV/mA
mV/mA
ns
Input Range 3 mA
(INxRANGE = 011)
Input Range 4 mA
(INxRANGE = 010)
Input Range 5 mA
(INxRANGE = 001)
Input Range 6 mA
(INxRANGE = 000)
Settling Time to 0.1%
V
IVCOUT
20
Preliminary Rev. 0.8
SILICON [ SILICON ]
