SiM3C1xx
Table 3.4. Reset and Supply Monitor
Parameter
Symbol
Conditions
Early Warning
Reset
Min
2.10
1.95
1.81
1.70
4.2
—
Typ
2.20
2.05
1.85
1.74
4.4
1.4
1
Max
2.30
2.1
Units
V
V
High Supply Monitor Threshold
(VDDHITHEN = 1)
V
VDDMH
DD
V
V
Low Supply Monitor Threshold
(VDDHITHEN = 0)
V
Early Warning
Reset
1.88
1.77
4.6
V
DD
VDDML
V
V
Supply Monitor Threshold
V
Early Warning
Rising Voltage on V
V
REGIN
VREGM
Power-On Reset (POR) Threshold
V
—
V
POR
DD
Falling Voltage on V
0.8
10
1.3
V
DD
V
Ramp Time
t
Time to V > 1.8 V
—
3000
100
µs
ms
DD
RMP
DD
Reset Delay from POR
t
Relative to V
>
DD
3
—
POR
V
POR
Reset Delay from non-POR source
t
Time between release
of reset source and
code execution
—
10
—
µs
RST
RESET Low Time to Generate Reset
t
50
—
—
—
1
ns
RSTL
Missing Clock Detector Response
Time (final rising edge to reset)
t
F
> 1 MHz
0.4
ms
MCD
AHB
Missing Clock Detector Trigger
Frequency
F
—
—
7.5
2
13
—
kHz
µs
MCD
MON
V
Supply Monitor Turn-On Time
t
DD
12
Preliminary Rev. 0.8
SILICON [ SILICON ]
