SI5338G-A-GM 参数 Datasheet PDF下载

Si5338

Table 5. Performance Characteristics (Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Phase Increment/Decrement

Update Time

Symbol

P

UPDATE

Test Condition

Pin control

MultiSynth output <18 MHz

Number of periods of

MultiSynth output frequency

R divider not used

R divider not used

Pin control

MultiSynth output >18 MHz

Pin control

MultiSynth output <18 MHz

Number of periods of

MultiSynth output frequency

MultiSynth Output < ~Fvco/8

MultiSynth Output < ~Fvco/8

Min

—

Typ

12

Max

—

Unit

Periods

Frequency Increment/

Decrement Step Size

Frequency Increment/

Decrement Range

Frequency Increment/

Decrement Update Time

Frequency Increment/

Decrement Update Time

f

STEP

f

RANGE

f

UPDATE

f

UPDATE

1

—

667

—

—

—

—

12

See

Note

350

—

—

ppm

MHz

ns

Periods

Spread Spectrum PP

Frequency Deviation

Spread Spectrum Modulation

Rate

SS

DEV

SS

DEV

0.1

30

—

—

5.0

63

%

kHz

Notes:

1.

Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.

2.

The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept

between 5 MHz and Fvco/8.

3.

Update rate via I

2

C is also limited by the time it takes to perform a write operation.

4.

Default value is 0.5% down spread.

5.

Default value is ~31.5 kHz.

Table 6. Input and Output Clock Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)

Frequency

Differential Voltage

Swing

Rise/Fall Time

Duty Cycle

f

IN

V

PP

t

R

/t

F

DC

710 MHz input

20%–80%

< 1 ns tr/tf

5

0.4

—

40

—

—

—

—

710

2.4

1.0

60

MHz

V

PP

ns

%

Notes:

1.

For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns

2.

Not in PLL bypass mode.

3.

For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns

4.

Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.

5.

Includes effect of internal series 22



resistor.

Rev. 0.6

7