SI5338G-A-GM 参数 Datasheet PDF下载

Si5338

Table 6. Input and Output Clock Characteristics (Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Input Impedance

Input Capacitance

Symbol

R

IN

C

IN

Test Condition

Min

10

—

Typ

—

3.5

Max

—

—

Units

k

pF

Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)

Frequency

Input Voltage

Input Voltage Swing

Rise/Fall Time

Duty Cycle

Input Capacitance

Output Clocks (Differential)

0.16

Frequency

LVPECL, LVDS

f

OUT

HCSL

V

OC

LVPECL Output Voltage

V

SEPP

V

OC

V

SEPP

V

OC

V

SEPP

V

OC

HCSL Output Voltage

V

SEPP

t

R

/t

F

DC

common mode

peak-to-peak single-

ended swing

common mode

peak-to-peak single-

ended swing

common mode

peak-to-peak single-

ended swing

common mode

peak-to-peak single-

ended swing

20%–80%

367

550

0.16

—

0.55

1.125

0.25

0.8

0.25

0.35

0.575

—

45

—

—

—

—

V

DDO

–1.45 V

0.8

1.2

0.35

0.875

0.35

0.375

0.725

—

—

350

473.33

710

250

—

0.96

1.275

0.45

0.95

0.45

0.400

0.85

450

55

MHz

MHz

MHz

MHz

V

V

PP

V

V

PP

V

V

PP

V

V

PP

ps

%

t

R

/t

F

DC

C

IN

f

IN

V

I

200 MHz

20%–80%

< 4 ns tr/tf

CMOS

5

–0.1

0.8

—

40

—

—

—

—

—

—

2.0

200

3.63

VDD+10%

2

60

—

MHz

V

Vpp

ns

%

pF

LVDS Output Voltage

(2.5/3.3 V)

LVDS Output Voltage

(1.8 V)

Rise/Fall Time

Duty Cycle

Notes:

1.

For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns

2.

Not in PLL bypass mode.

3.

For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns

4.

Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.

5.

Includes effect of internal series 22



resistor.

8

Rev. 0.6