Si5338
Table 5. Performance Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
PLL Acquisition Time
PLL Lock Range
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
CLKIN Loss of Signal Detect
Time
CLKIN Loss of Signal Release
Time
PLL Loss of Lock Detect Time
POR to Output Clock Valid
(Pre-programmed Devices)
Input-to-Output Propagation
Delay
Output-Output Skew
POR to I
2
C Ready
Programmable Initial
Phase Offset
Phase Increment/Decrement
Accuracy
Phase Increment/Decrement
Range
Frequency range for phase
increment/decrement
Phase Increment/Decrement
Update Time
Symbol
t
ACQ
f
LOCK
f
BW
f
RES
t
LOS
t
LOSRLS
t
LOL
t
RDY
t
PROP
t
DSKEW
Test Condition
Min
—
5000
—
Typ
—
—
1.6
0
2.6
0.2
5
—
2.5
—
—
—
—
—
—
—
Max
25
—
—
1
5
1
10
2
—
100
15
+45
20
+45
350
—
Unit
ms
ppm
MHz
ppb
µs
µs
ms
ms
ns
ps
ms
ns
ps
ns
MHz
ns
Output frequency < Fvco/8
0
—
0.01
—
—
Buffer Mode
(PLL Bypass)
Rn divider = 1
1
—
—
—
P
OFFSET
P
STEP
P
RANGE
f
PRANGE
P
UPDATE
Pin control
MultiSynth output >18 MHz
–45
—
–45
—
667
Notes:
1.
Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.
2.
The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3.
Update rate via I
2
C is also limited by the time it takes to perform a write operation.
4.
Default value is 0.5% down spread.
5.
Default value is ~31.5 kHz.
6
Rev. 0.6
SILABS [ SILICON LABORATORIES ]
