Si3056
Si3018/19/10
Register 23. Ring Validation Control 2
Bit
D7
RDLY[2]
R/W
D6
D5
D4
D3
D2
D1
RCC[2:0]
R/W
D0
Name
Type
RTO[3:0]
R/W
Reset settings = 0010_1101
Bit
Name
Function
7
RDLY[2]
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0 ms
256 ms
512 ms
0
0
0
.
00
01
10
.
.
1
11
1792 ms
6:3
RTO[3:0]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring thresh-
old crossing.
RTO[3:0]
Ring Timeout
80 ms
128 ms
256 ms
0000
0001
0010
.
.
.
1111
1920 ms
2:0
RCC[2:0]
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
000
Ring Confirmation Count Time
100 ms
150 ms
200 ms
256 ms
384 ms
512 ms
640 ms
1024 ms
001
010
011
100
101
110
111
66
Rev. 1.05
SILICON [ SILICON ]
