Si3056
Si3018/19/10
Register 24. Ring Validation Control 3
Bit
D7
D6
D5
D4
D3
RAS[5:0]
R/W
D2
D1
D0
Name
Type
RNGV
R/W
R
Reset settings = 0001_1001
Bit
Name
Function
7
RNGV
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-power
mode.
6
Reserved
RAS[5:0]
Reserved and may read either a 1 or 0.
5:0
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
1
-------------------------------------------
RMX[5:0] ≥ RAS[5:0] –
, RMX ≤ RAS
2 × f_min × 2 ms
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
Rev. 1.05
67
SILICON [ SILICON ]
