Si3056
Si3018/19/10
Register 22. Ring Validation Control 1
Bit
D7
D6
D5
D4
D3
D2
RMX[5:0]
R/W
D1
D0
Name
Type
RDLY[1:0]
R/W
Reset settings = 1001_0110
Bit
Name
Function
7:6
RDLY[1:0]
Ring Delay Bits 1 and 0.
These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0 ms
0
0
0
.
.
.
00
01
10
256 ms
512 ms
1
11
1792 ms
5:0
RMX[5:0]
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
1
--------------------------------------------
RMX[5:0] ≥ RAS[5:0] –
, RMX ≤ RAS
2 × f_max × 2 ms
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
Rev. 1.05
65
SILICON [ SILICON ]
