Si3056
Si3018/19/10
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
SDI
R/W
SDO
Figure 30. Secondary Communication Data Format—Write Cycle
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master FSYNC
32 SCLKs
32 SCLKs
Master FSD/
Slave1 FSYNC
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SDO [0]
SDO[15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 31. Daisy Chaining of a Single Slave (Pulse FSD)
Rev. 1.05
43
SILICON [ SILICON ]
