Si3056
Si3018/19/10
SRC[3:0] bits (Register 7, bits 3:0) must be The Si3056 also supports an additional powerdown
programmed with the proper sample rate value before mode. When both the PDN (Register 6, bit 3) and PDL
the sampled line data is valid. The SCLK pin of the (Register 6, bit 4) bits are set, the chipset enters a
slave is a no connect in this configuration.
complete powerdown mode and draws negligible
current (deep sleep mode). Turn off the PLL2 before
entering deep sleep mode (i.e., set Register 9 to 0 and
then Register 6 to 0x18). In this mode, the Si3056 is
non-functional. Normal operation is restored by the
same process for taking the DAA out of sleep mode.
The delay between FSYNC input and delayed frame
sync output (RGDT/FSD/M1) is 16 SCLK periods. The
RGDT/FSD/M1 output has a waveform identical to the
FSYNC signal in serial mode 0. In addition, the LSB of
SDO is set to 0 by default for all devices in serial
mode 2.
5.29. Calibration
5.28. Power Management
The Si3056 initiates two auto-calibrations by default
when the device goes off-hook or experiences a loss in
line power. A 17 ms resistor calibration is performed to
allow circuitry internal to the DAA to adjust to the exact
line conditions present at that time. This resistor
calibration can be disabled by setting the RCALD bit
(Register 25, bit 5). A 256 ms ADC calibration is also
performed to remove offsets that might be present in the
on-chip A/D converter which could affect the A/D
dynamic range. The ADC auto-calibration is initiated
after the DAA dc termination stabilizes, and the resistor
calibration completes. Because large variations in line
conditions and line card behavior exist, it could be
beneficial to use manual calibration instead of auto-
calibration.
The Si3056 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
PDN and PDL bits (Register 6) control the power
management modes.
On powerup, or following a reset, the Si3056 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3056 is operational, except for the
isolation link. No communication between the Si3056
and line-side device can occur during reset operation.
Bits associated with the line-side device are not valid in
this mode.
In typical applications, the DAA will predominantly be
operated in normal mode. In this mode, the PDL and
PDN bits are cleared. The Si3056 is operational and the
isolation link is passing information between the Si3056
and the line-side device.
Execute manual ADC calibration as close as possible to
256 ms before valid transmit/receive data is expected.
Take the following steps to implement manual ADC
calibration:
The Si3056 supports a low-power sleep mode to
support ring validation and wake-on-ring features. The
clock generator registers 7, 8, and 9 must be
1. The CALD (auto-calibration disable—Register 17) bit
must be set to 1.
programmed with valid, non-zero values and the PDL 2. The MCAL (manual calibration) bit must be toggled
bit must be clear before enabling sleep mode. The PDN
bit must then be set. When the Si3056 is in sleep mode
the MCLK signal must remain active. In low-power
sleep mode with MCLK active, the Si3056 is non-
functional except for the isolation link and the RGDT
signal. To take the Si3056 out of sleep mode, pulse the
reset pin (RESET) low.
to 1 and then 0 to begin and complete the
calibration.
3. The calibration is completed in 256 ms.
5.30. In-Circuit Testing
With the Si3056’s advanced design the designer can
determine system functionality during production line
In summary, the powerdown/up sequence for sleep tests, and during support for end-user diagnostics. Four
mode is as follows:
loopback modes allow thorough coverage of system
components. Four of the test modes require a line-side
power source. Although a standard phone line can be
used, the test circuit in Figure 1 on page 6 is adequate.
In addition, an off-hook sequence must be performed to
connect the power source to the line-side device.
For the start-up loopback test mode, line-side power is
not necessary and no off-hook sequence is required.
The start-up test mode is enabled by default. When the
PDL bit (Register 6, bit 4) is set (the default case), the
line-side is in a powerdown mode and the DSP-side is
in a digital loop-back mode. Data received on SDI
1. Ensure that Registers 7, 8, and 9 have valid non-
zero values, and ensure the PDL bit (Register 6, bit
4) is cleared.
2. Set the PDN bit (Register 6, bit 3).
3. The device is now in sleep mode. MCLK must stay
active.
4. To exit sleep mode, reset the Si3056 by pulsing the
RESET pin.
5. Program registers to desired settings.
Rev. 1.05
39
SILICON [ SILICON ]
