Si3056
Si3018/19/10
Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Min
244
—
Typ
Max
—
Unit
ns
%
Cycle time, SCLK
t
1/256 Fs
c
SCLK Duty Cycle
t
50
—
—
—
—
—
—
—
—
dty
Delay Time, SCLK↑ to FSYNC↓
Delay Time, SCLK↑ to SDO Valid
Delay Time, SCLK↑ to FSYNC↑
Setup Time, SDI Before SCLK ↓
Hold Time, SDI After SCLK ↓
Setup Time, FC↑ Before SCLK↑
Hold time, FC↑ After SCLK↑
t
—
20
20
20
—
ns
ns
ns
ns
ns
ns
ns
d1
d2
d3
t
t
—
—
t
25
20
40
40
su
t
—
h
t
—
sfc
hfc
t
—
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
tc
VOH
VOL
SCLK
td1
td3
FSYNC
(mode 0)
td3
FSYNC
(mode 1)
td2
16-Bit
SDO
D15
D14
D14
D1
D1
DD00
D0
tsu
th
16-Bit
SDI
D15
tsfc
thfc
FC
Figure 3. Serial Interface Timing Diagram (DCE = 0)
Rev. 1.05
11
SILICON [ SILICON ]
