Si3056
Si3018/19/10
Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
1,2
Symbol
Min
Typ
Max
Unit
Parameter
Cycle Time, SCLK
SCLK Duty Cycle
t
244
—
—
—
—
—
—
—
25
20
1/256 Fs
—
—
20
20
20
20
20
20
—
—
ns
%
c
t
50
—
—
—
—
—
—
—
—
dty
Delay Time, SCLK↑ to FSYNC↑
Delay Time, SCLK↑ to FSYNC↓
Delay Time, SCLK↑ to SDO valid
Delay Time, SCLK↑ to SDO Hi-Z
Delay Time, SCLK↑ to FSD↓
Delay Time, SCLK↑ to FSD↑
Setup Time, SDO Before SCLK↓
Hold Time, SDO After SCLK↓
Notes:
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
d1
d2
d3
d4
d5
d6
t
su
t
h
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. See "5.27.Multiple Device Support" on page 38 for functional details.
32 SCLKs
16 SCLKs
16 SCLKs
tc
SCLK
td1
td2
td2
FSYNC
(mode 1)
td2
td6
td2
FSYNC
(mode 0)
td3
tsu
D15
th
td4
SDO
(master)
D14
D13
D0
td3
SDO
D15
(slave 1)
td5
FSYNC
(Mode 0)
td5
FSYNC
(Mode 1)
tsu
th
D14
SDI
D15
D13
D0
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
12
Rev. 1.05
SILICON [ SILICON ]
