Si1000/1/2/3/4/5
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
= 1.4 mA,
Min
Typ
—
Max
0.6
Units
V
RST Output Low Voltage
RST Input High Voltage
I
—
OL
V
V
V
V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
V
– 0.6
—
—
V
DD
DD
DD
DD
DD
0.7 x V
—
—
—
V
DD
RST Input Low Voltage
—
0.6
V
—
—
0.3 x V
V
DD
RST Input Pullup Current
VDD_MCU Monitor
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
—
4
20
—
30
µA
Early Warning
Reset Trigger
1.8
1.7
1.85
1.75
1.9
1.8
V
Threshold (V
)
RST
(all power modes except Sleep)
V
On
Ramp Time for Power
V
Ramp from 0–0.9 V
DD
—
—
3
ms
V
DD
VDD Monitor Threshold
(V
Initial Power-On (V Rising)
Brownout Condition (V Falling)
Recovery from Brownout (V Rising)
—
0.7
—
0.75
0.8
0.95
—
0.9
—
DD
)
POR
DD
DD
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650
1000
µs
Minimum System Clock w/ System clock frequency which triggers
—
7
10
kHz
Missing Clock Detector
Enabled
a missing clock detector timeout
Reset Time Delay
Delay between release of any reset
source and code
—
10
—
—
—
µs
µs
execution at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
V
V
Monitor Turn-on Time
—
—
300
7
—
—
ns
DD
Monitor Supply
µA
DD
Current
Rev. 1.0
57
SILICON [ SILICON ]
