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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
Offset = 256 PCA0CPL5+ 256 – PCA0L  
Equation 28.5. Watchdog Timer Offset in PCA Clocks  
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and  
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is  
enabled.  
28.4.2. Watchdog Timer Usage  
To configure the WDT, perform the following tasks:  
Disable the WDT by writing a 0 to the WDTE bit.  
Select the desired PCA clock source (with the CPS2CPS0 bits).  
Load PCA0CPL5 with the desired WDT update offset value.  
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle  
mode).  
Enable the WDT by setting the WDTE bit to 1.  
Reset the WDT timer by writing to PCA0CPH5.  
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog  
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the  
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing  
the WDTE bit.  
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by  
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 28.5, this results in a WDT  
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 28.3 lists some example time-  
out intervals for typical system clocks.  
Table 28.3. Watchdog Timer Timeout Intervals1  
System Clock (Hz)  
24,500,000  
PCA0CPL5  
255  
Timeout Interval (ms)  
32.1  
16.2  
24,500,000  
128  
24,500,000  
32  
4.1  
2
3,062,500  
255  
257  
2
3,062,500  
128  
129.5  
33.1  
2
3,062,500  
32  
32,000  
32,000  
32,000  
255  
24576  
12384  
3168  
128  
32  
Notes:  
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value  
of 0x00 at the update time.  
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.  
364  
Rev. 1.0