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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
28.3.5.1. 8-Bit Pulse Width Modulator Mode  
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-  
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the  
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the  
CEXn output will be reset (see Figure 28.8). Also, when the counter/timer low byte (PCA0L) overflows from  
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare  
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the  
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width  
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit  
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow  
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in  
Equation 28.2.  
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-  
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the  
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.  
256 – PCA0CPHn  
Duty Cycle = ---------------------------------------------------  
256  
Equation 28.2. 8-Bit PWM Duty Cycle  
Using Equation 28.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is  
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.  
Write to  
0
PCA0CPLn  
ENB  
Reset  
PCA0CPHn  
PCA0CPLn  
Write to  
PCA0CPHn  
ENB  
COVF  
1
PCA0PWM  
A E C  
R C O  
S O V  
E V F  
L
PCA0CPMn  
C C  
L L  
S S  
E E  
L L  
1 0  
P E C C M T P E  
W C A A A O W C  
M O P P T G M C  
1 M P N n n n F  
6 n n n  
n
n
0
x
0
0
0
0 0 x 0  
x
8-bit  
Comparator  
match  
SET  
CLR  
CEXn  
Enable  
S
R
Q
Q
Crossbar  
Port I/O  
PCA Timebase  
PCA0L  
Overflow  
Figure 28.8. PCA 8-Bit PWM Mode Diagram  
360  
Rev. 1.0  
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