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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
28.4. Watchdog Timer Mode  
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used  
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified  
limit. The WDT can be configured and enabled/disabled as needed by software.  
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-  
ule 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be  
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some  
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset  
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-  
ally re-configured and re-enabled if it is used in the system).  
28.4.1. Watchdog Timer Operation  
While the WDT is enabled:  
PCA counter is forced on.  
Writes to PCA0L and PCA0H are not allowed.  
PCA clock source bits (CPS2CPS0) are frozen.  
PCA Idle control bit (CIDL) is frozen.  
Module 5 is forced into software timer mode.  
Writes to the Module 5 mode register (PCA0CPM5) are disabled.  
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run  
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but  
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while  
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a  
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is  
loaded into PCA0CPH5 (See Figure 28.11).  
PCA0MD  
C W W  
D D  
D T  
C C C E  
P P P C  
S S S F  
2 1 0  
PCA0CPH5  
I
L
L E C  
K
8-bit  
Comparator  
Match  
Reset  
Enable  
PCA0L Overflow  
PCA0CPL5  
8-bit Adder  
PCA0H  
Adder  
Enable  
Write to  
PCA0CPH2  
Figure 28.11. PCA Module 5 with Watchdog Timer Enabled  
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This  
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the  
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The  
total offset is then given (in PCA clocks) by Equation 28.5, where PCA0L is the value of the PCA0L register  
at the time of the update.  
Rev. 1.0  
363