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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
28.1. PCA Counter/Timer  
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte  
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches  
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.  
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.  
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2CPS0 bits in the PCA0MD  
register select the timebase for the counter/timer as shown in Table 28.1.  
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is  
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in  
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically  
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-  
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the  
CPU is in Idle mode.  
Table 28.1. PCA Timebase Input Options  
CPS2  
CPS1  
CPS0  
Timebase  
0
0
0
0
0
0
1
1
0
1
0
1
System clock divided by 12  
System clock divided by 4  
Timer 0 overflow  
High-to-low transitions on ECI (max rate = system clock divided  
by 4)  
1
1
1
1
0
0
1
1
0
1
0
1
System clock  
*
External oscillator source divided by 8  
Reserved  
Reserved  
Note: External oscillator source divided by 8 is synchronized with the system clock.  
IDLE  
PCA0MD  
PCA0CN  
C W W C C C E  
C C C C C C C C  
F R C C C C C C  
F F F F F F  
I
D D P P P C  
D T  
L E C  
L
S S S F  
2 1 0  
5 4 3 2 1 0  
To SFR Bus  
PCA0L  
read  
K
Snapshot  
Register  
SYSCLK/12  
SYSCLK/4  
000  
001  
010  
011  
100  
101  
0
Timer 0 Overflow  
ECI  
Overflow  
To PCA Interrupt System  
PCA0H  
PCA0L  
1
CF  
SYSCLK  
External Clock/8  
To PCA Modules  
Figure 28.2. PCA Counter/Timer Block Diagram  
Rev. 1.0  
353