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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
27.3.3. Comparator 1/External Oscillator Capture Mode  
The Capture Mode in Timer 3 allows either Comparator 1 or the external oscillator period to be measured  
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator  
period can also be compared against each other.  
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this  
mode, T3SPLIT should be set to 0, as the full 16-bit timer is used.  
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge  
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the  
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)  
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-  
ence between two successive timer capture values, the Comparator 1 or external clock period can be  
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture  
clock to achieve an accurate reading.  
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-  
ture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive  
captures is 350 counts, then the Comparator 1 period is:  
350 x (1 / 24.5 MHz) = 14.2 µs.  
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or  
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the  
capacitance of a Touch Sense Switch.  
T3XCLK[1:0]  
CKCON  
T
3
T T  
T
2
T
1
T S S  
0 C C  
3
2
M M M M M M A A  
SYSCLK / 12  
External Clock / 8  
Comparator 1  
X0  
H L H L  
1 0  
01  
11  
0
1
TCLK  
TR3  
TMR3L  
TMR3H  
Capture  
SYSCLK  
T3XCLK1  
TF3CEN  
TF3H  
TF3L  
Interrupt  
TMR3RLL TMR3RLH  
TF3LEN  
TF3CEN  
T3SPLIT  
TR3  
T3XCLK1  
T3XCLK0  
Comparator 1  
0
1
External Clock / 8  
Figure 27.9. Timer 3 Capture Mode Block Diagram  
348  
Rev. 1.0