Si1000/1/2/3/4/5
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
T3MH
T3XCLK[1:0] TMR3H Clock
Source
T3ML
T3XCLK[1:0] TMR3L Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
Comparator 1
Reserved
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
Comparator 1
Reserved
External Clock / 8
SYSCLK
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M M M M M M A A
Reload
TMR3RLH
H L H L
1 0
SYSCLK / 12
Comparator 1
00
0
1
01
11
TCLK
TF3H
TF3L
TMR3H
Interrupt
TR3
TF3LEN
TF3CEN
T3SPLIT
TR3
External Clock / 8
Reload
T3XCLK1
T3XCLK0
TMR3RLL
SYSCLK
1
0
TCLK
TMR3L
To ADC
Figure 27.8. Timer 3 8-Bit Mode Block Diagram.
Rev. 1.0
347
SILICON [ SILICON ]
