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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 27.8. TMR2CN: Timer 2 Control  
Bit  
7
TF2H  
R/W  
0
6
TF2L  
R/W  
0
5
TF2LEN  
R/W  
0
4
3
2
1
0
Name  
Type  
Reset  
TF2CEN T2SPLIT  
TR2  
R/W  
0
T2XCLK[1:0]  
R/W  
R/W  
0
R/W  
0
0
0
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable  
Bit  
Name  
Function  
7
TF2H  
Timer 2 High Byte Overflow Flag.  
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit  
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the  
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the  
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.  
6
5
TF2L  
Timer 2 Low Byte Overflow Flag.  
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will  
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not  
automatically cleared by hardware.  
TF2LEN  
Timer 2 Low Byte Interrupt Enable.  
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts  
are also enabled, an interrupt will be generated when the low byte of Timer 2 over-  
flows.  
4
3
TF2CEN  
T2SPLIT  
Timer 2 Capture Enable.  
When set to 1, this bit enables Timer 2 Capture Mode.  
Timer 2 Split Mode Enable.  
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,  
Timer 2 operates in 16-bit auto-reload mode.  
2
TR2  
Timer 2 Run Control.  
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables  
TMR2H only; TMR2L is always enabled in split mode.  
1:0 T2XCLK[1:0] Timer 2 External Clock Select.  
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If  
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer  
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be  
used to select between the “external” clock and the system clock for either timer.  
Note: External clock sources are synchronized with the system clock.  
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.  
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.  
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.  
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.  
Rev. 1.0  
343