Si1000/1/2/3/4/5
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
T2XCLK[1:0]
TMR2H Clock
Source
T2ML
T2XCLK[1:0]
TMR2L Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock / 8
Reserved
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
Comparator 0
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T2XCLK[1:0]
MMMMMM A A
Reload
TMR2RLH
To SMBus
H L H L
1 0
SYSCLK / 12
00
0
01
11
SmaRTClock / 8
Comparator 0
TCLK
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
TMR2H
Interrupt
TR2
1
Reload
TMR2RLL
T2XCLK
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
Figure 27.5. Timer 2 8-Bit Mode Block Diagram
Rev. 1.0
341
SILICON [ SILICON ]
