Si1000/1/2/3/4/5
27.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer
2
(TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a Touch Sense Switch.
T2XCLK[1:0]
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMM A A
SYSCLK/12
Comparator 0
SmaRTClock/8
X0
H L H L
1 0
01
11
0
1
TCLK
TR2
TMR2L
TMR2H
Capture
SYSCLK
T2XCLK1
TF2CEN
TF2H
TF2L
Interrupt
TMR2RLL TMR2RLH
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
SmaRTClock/8
Comparator 0
0
1
Figure 27.6. Timer 2 Capture Mode Block Diagram
342
Rev. 1.0
SILICON [ SILICON ]
