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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration  
Bit  
7
6
5
4
3
2
1
0
ENSMB  
INH  
BUSY  
EXTHOLD SMBTOE SMBFTE  
SMBCS[1:0]  
R/W  
Name  
Type  
Reset  
R/W  
0
R/W  
0
R
0
R/W  
0
R/W  
0
R/W  
0
0
0
SFR Page = 0x0; SFR Address = 0xC1  
Bit  
Name  
Function  
7
ENSMB  
SMBus Enable.  
This bit enables the SMBus interface when set to 1. When enabled, the interface  
constantly monitors the SDA and SCL pins.  
6
INH  
SMBus Slave Inhibit.  
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave  
events occur. This effectively removes the SMBus slave from the bus. Master Mode  
interrupts are not affected.  
5
4
BUSY  
SMBus Busy Indicator.  
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to  
logic 0 when a STOP or free-timeout is sensed.  
EXTHOLD  
SMBus Setup and Hold Time Extension Enable.  
This bit controls the SDA setup and hold times according to Table 24.2.  
0: SDA Extended Setup and Hold Times disabled.  
1: SDA Extended Setup and Hold Times enabled.  
3
SMBTOE  
SMBus SCL Timeout Detection Enable.  
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces  
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.  
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload  
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,  
and the Timer 3 interrupt service routine should reset SMBus communication.  
2
SMBFTE  
SMBus Free Timeout Detection Enable.  
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain  
high for more than 10 SMBus clock source periods.  
1:0 SMBCS[1:0]  
SMBus Clock Source Selection.  
These two bits select the SMBus clock source, which is used to generate the SMBus  
bit rate. The selected device should be configured according to Equation 24.1.  
00: Timer 0 Overflow  
01: Timer 1 Overflow  
10:Timer 2 High Byte Overflow  
11: Timer 2 Low Byte Overflow  
Rev. 1.0  
293