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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically  
necessary when SYSCLK is above 10 MHz.  
Table 24.2. Minimum SDA Setup and Hold Times  
EXTHOLD  
Minimum SDA Setup Time  
– 4 system clocks  
Minimum SDA Hold Time  
0
T
3 system clocks  
low  
or  
1 system clock + s/w delay*  
11 system clocks  
1
12 system clocks  
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using  
software acknowledgement, the s/w delay occurs between the time SMB0DAT or  
ACK is written and when SI is cleared. Note that if SI is cleared in the same write  
that defines the outgoing ACK value, s/w delay is zero.  
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low  
timeouts (see Section “24.3.4. SCL Low Timeout” on page 289). The SMBus interface will force Timer 3 to  
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine  
should be used to reset SMBus communication by disabling and re-enabling the SMBus.  
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will  
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see  
Figure 24.4).  
292  
Rev. 1.0