Si1000/1/2/3/4/5
SFR Definition 22.1. SPI1CFG: SPI Configuration
Bit
7
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
2
1
0
Name SPIBSY
Type
R
0
R
0
R
1
R
1
R
1
Reset
SFR Page = 0x0; SFR Address = 0x84
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress.
6
5
MSTEN
CKPHA
CKPOL
Master Mode Enable.
When set to ‘1’, enables master mode. This bit must be set to 1 to communicate
with the EZRadioPRO peripheral.
SPI Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
*
4
SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3:0
Reserved.
Read = 0000, Write = don’t care.
Note: In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum
settling time for the slave device. See Table 22.2 for timing parameters.
234
Rev. 1.0
SILICON [ SILICON ]
