Si1000/1/2/3/4/5
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers
without having to re-send the SPI address. When the NSS bit is held low while continuing to send SCK
pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address.
An example burst write transaction is illustrated in Figure 22.4 and a burst read in Figure 22.5. As long as
NSS is held low, input data will be latched into the transceiver every eight SCK cycles.
First Bit
Last Bit
RW
=1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X =X =X =X =X =X =X =X =X
MOSI
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
SCL
nSEL
NSS
Figure 22.4. SPI Timing—Burst Write Mode
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
MOSI
SCLK
SCL
First Bit
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
MISO
NSS
nSEL
Figure 22.5. SPI Timing—Burst Read Mode
Rev. 1.0
231
SILICON [ SILICON ]
