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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
22.4. EZRadioPRO Serial Interface Interrupt Sources  
When SPI1 interrupts are enabled, the following flags will generate an interrupt when they are set to logic  
1:  
All of the following bits must be cleared by software.  
1. The SPI Interrupt Flag, SPIFn (SPInCN.7) is set to logic 1 at the end of each byte transfer.  
This flag can occur in all SPIn modes.  
2. The Write Collision Flag, WCOLn (SPInCN.6) is set to logic 1 if a write to SPInDAT is  
attempted when the transmit buffer has not been emptied to the SPI shift register. When this  
occurs, the write to SPInDAT will be ignored, and the transmit buffer will not be written.This  
flag can occur in all SPIn modes.  
3. The Mode Fault Flag MODFn (SPInCN.5) is set to logic 1 when SPIn is configured as a  
master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs,  
the MSTENn and SPIENn bits in SPI0CN are set to logic 0 to disable SPIn and allow another  
master device to access the bus.  
4. The Receive Overrun Flag RXOVRNn (SPInCN.4) is set to logic 1 when configured as a slave,  
and a transfer is completed and the receive buffer still holds an unread byte from a previous  
transfer. The new byte is not transferred to the receive buffer, allowing the previously received  
data byte to be read. The data byte which caused the overrun is lost.  
22.5. Serial Clock Phase and Polarity  
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI  
Configuration Register (SPI1CFG). The CKPHA bit (SPI1CFG.5) selects one of two clock phases (edge  
used to latch the data). The CKPOL bit (SPI1CFG.4) selects between an active-high or active-low clock.  
Both CKPOL and CKPHA must be set to zero in order to communicate with the EZRadioPRO peripheral.  
The SPI1 Clock Rate Register (SPI1CKR) as shown in SFR Definition 22.3 controls the master mode  
serial clock frequency. When the SPI is configured as a master, the maximum data transfer rate (bits/sec)  
is one-half the system clock frequency or 12.5 MHz, whichever is slower.  
SCK  
(CKPOL=0, CKPHA=0)  
SCK  
(CKPOL=0, CKPHA=1)  
SCK  
(CKPOL=1, CKPHA=0)  
SCK  
(CKPOL=1, CKPHA=1)  
MISO/MOSI  
MSB  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
NSS (Must Remain High  
in Multi-Master Mode)  
Figure 22.6. Master Mode Data/Clock Timing  
232  
Rev. 1.0