Si1000/1/2/3/4/5
Data
Address
MSB
MSB
LSB
RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
MOSI
SDI
SCLK
NSS
nSEL
Figure 22.2. SPI Timing
Table 22.1. Serial Interface Timing Parameters
Symbol
Parameter
Min
Diagram
(nsec)
t
Clock high time
Clock low time
Data setup time
Data hold time
40
40
20
20
20
CH
t
CL
DS
DH
DD
SCL
SCLK
t
tSS
tCL tCH
tDS tDH tDD
tSH tDE
t
t
Output data delay
time
MSODSI I
SDO
MISO
t
t
Output enable time
Output disable time
Select setup time
Select hold time
20
50
20
50
80
EN
tEN
tSW
DE
nSEL
NSS
t
SS
SH
t
t
Select high period
SW
To read back data from the transceiver, the R/W bit must be set to 0 followed by the 7-bit address of the
register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the MOSI pin
when R/W = 0. The next eight negative edge transitions of the SCK signal will clock out the contents of the
selected register. The data read from the selected register will be available on the MISO output. The READ
function is shown in Figure 22.3. After the READ function is completed the MISO signal will remain at
either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When NSS goes high the
MISO output pin will be pulled high by internal pullup.
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
MOSI
SCLK
SCL
First Bit
Last Bit
SDO
MISO
D7 D6 D5 D4 D3 D2 D1 D0
NSS
nSEL
Figure 22.3. SPI Timing—READ Mode
230
Rev. 1.0
SILICON [ SILICON ]
