Si1000/1/2/3/4/5
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si1000/1/2/3/4/5's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
Si1000/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the Si1000/1/2/3/4/5 device
family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed description of each register.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN
F0
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
P1MDIN P2MDIN SMB0ADR SMB0ADM EIP1 EIP2
B
P0MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF EIE1 EIE2
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0PWM
D0 PSW
C8 TMR2CN REG0CN TMR2RLL TMR2RLH
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH
B8 IP IREF0CN ADC0AC ADC0MX ADC0CF
B0 SPI1CN OSCXCN OSCICN OSCICL
REF0CN PCA0CPL5 PCA0CPH5 P0SKIP
P1SKIP
TMR2H
P2SKIP
PCA0CPM5
ADC0LTH
ADC0H
P0MAT
P1MAT
TMR2L
ADC0LTL
ADC0L
P0MASK
P1MASK
FLKEY
PMU0CF
FLSCL
A8
A0
IE
CLKSEL
EMI0CN
Reserved RTC0ADR RTC0DAT
RTC0KEY
Reserved
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
P2MDOUT SFRPAGE
98 SCON0
90 P1
88 TCON
SBUF0
CPT1CN
CPT0CN
CPT1MD
TMR3L
TH0
CPT0MD
TMR3H
TH1
CPT1MX
DC0CF
CKCON
SPI1DAT
6(E)
CPT0MX
DC0CN
PSCTL
PCON
7(F)
TMR3CN TMR3RLL TMR3RLH
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
80
P0
SPI1CFG
4(C)
SPI1CKR
5(D)
0(8)
1(9)
(bit addressable)
Rev. 1.0
123
SILICON [ SILICON ]
