Si1000/1/2/3/4/5
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The Si1000/1/2/3/4/5 implements 64 kB (Si1000/2)
or 32 kB (Si1001/3) of this program memory space as in-system, re-programmable Flash memory, orga-
nized in a contiguous block from addresses 0x0000 to 0xFBFF (Si1000/2) or 0x7FFF (Si1001/3). The
address 0xFBFF (Si1000/2) or 0x7FFF (Si1001/3) serves as the security lock byte for the device. Any
addresses above the lock byte are reserved.
Si1000/2
(SFLE=0)
Si1001/3
(SFLE=0)
0xFFFF
0xFFFF
Reserved Area
0xFC00
0xFBFF
Unpopulated
Address Space
(Reserved)
Lock Byte
0xFBFE
Lock Byte Page
0xF800
0xF7FF
0x8000
0x7FFF
Lock Byte
Si1000/2
Si1001/3
(SFLE=1)
0x7FFE
Lock Byte Page
Flash Memory Space
0x7C00
0x7BFF
0x03FF
0x0000
Flash Memory Space
Scratchpad
(Data Only)
0x0000
0x0000
Figure 9.2. Flash Program Memory Map
9.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
Si1000/1/2/3/4/5 devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the Si1000/1/2/3/4/5 to update program code and use the program
memory space for non-volatile data storage. Refer to Section “13. Flash Memory” on page 141 for further
details.
9.2. Data Memory
The Si1000/1/2/3/4/5 device family includes 4352 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 9.1 for reference.
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
Rev. 1.0
119
SILICON [ SILICON ]
