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SI1005-C-GM 参数 Datasheet PDF下载

SI1005-C-GM图片预览
型号: SI1005-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 8.6. PSW: Program Status Word  
Bit  
7
6
5
4
3
2
1
0
CY  
AC  
F0  
RS[1:0]  
R/W  
OV  
F1  
PARITY  
Name  
Type  
Reset  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R
0
0
0
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable  
Bit  
Name  
Function  
7
CY  
Carry Flag.  
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-  
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.  
6
AC  
Auxiliary Carry Flag.  
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a  
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-  
metic operations.  
5
F0  
User Flag 0.  
This is a bit-addressable, general purpose flag for use under software control.  
4:3  
RS[1:0] Register Bank Select.  
These bits select which register bank is used during register accesses.  
00: Bank 0, Addresses 0x00-0x07  
01: Bank 1, Addresses 0x08-0x0F  
10: Bank 2, Addresses 0x10-0x17  
11: Bank 3, Addresses 0x18-0x1F  
2
OV  
Overflow Flag.  
This bit is set to 1 under the following circumstances:  
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.  
A MUL instruction results in an overflow (result is greater than 255).  
A DIV instruction causes a divide-by-zero condition.  
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all  
other cases.  
1
0
F1  
User Flag 1.  
This is a bit-addressable, general purpose flag for use under software control.  
PARITY Parity Flag.  
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared  
if the sum is even.  
Rev. 1.0  
117