C8051F52x-53x
Table 18.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 18.6 and Figure 18.7)
T
T
T
T
1 x T
SYSCLK
SCK High Time
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
1 x T
SCK Low Time
SYSCLK
MISO Valid to SCK Sample Edge
SCK Sample Edge to MISO Change
20
0
MIH
Slave Mode Timing* (See Figure 18.8 and Figure 18.9)
T
T
T
T
T
T
T
T
T
2 x T
2 x T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYSCLK
4 x T
—
SEZ
SDZ
CKH
CKL
SIS
SYSCLK
4 x T
—
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
SIH
SOH
SYSCLK
4 x T
—
SYSCLK
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK) in ns.
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
Rev. 0.3
183
SILICON [ SILICON ]
