C8051F52x-53x
18. Enhanced Serial Peripheral Interface (SPI0)
The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas-
ters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select
SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding conten-
tion on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general pur-
pose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
Pin Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 18.1. SPI Block Diagram
Rev. 0.3
171
SILICON [ SILICON ]
