C8051F52x-53x
13.2.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum V rise time specification of 1 ms is met. If the system cannot
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meet this rise time specification, then add an external V brownout circuit to the RST pin of
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the device that holds the device in reset until V
drops below 2.7 V.
reaches 2.7 V and re-asserts RST if V
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3. Enable the on-chip V monitor and enable the V monitor as a reset source as early in code
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as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-
based systems, this will involve modifying the startup code added by the 'C' compiler. See your
compiler documentation for more details. Make certain that there are no delays in software
between enabling the V
monitor and enabling the V
monitor as a reset source. Code
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examples showing this can be found in “AN201: Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the V
monitor and enable the V
monitor as a
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reset source inside the functions that write and erase Flash memory. The V monitor enable
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instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
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