C8051F50x-F51x
Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled) (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
SETB C
SETB bit
CPL C
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
1
2
2
2
2
2
2
2
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
2/(4-6)*
2/(4-6)*
3/(5-7)*
3/(5-7)*
3/(5-7)*
JNC rel
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
2
3
1
1
2
3
2
1
2
2
3
3
3
4-6*
5-7*
6-8*
6-8*
4-6*
5-7*
4-6*
3-5*
2/(4-6)*
2/(4-6)*
4/(6-8)*
3/(6-8)*
3/(5-7)*
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
4/(6-8)*
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
2/(4-6)*
3/(5-7)*
1
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 15.3).
Rev. 1.1
91
SILICON [ SILICON ]
