C8051F50x-F51x
DATA BUS
ACCUMULATOR
B
REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
SRAM
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
DATA POINTER
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 11.1. CIP-51 Block Diagram
With the CIP-51's maximum system clock at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute
1
2
2/3
5
3
3/4
7
4
3
4/5
1
5
2
8
1
Number of Instructions
26
50
14
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “28. C2 Interface” on page 306.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
Rev. 1.1
87
SILICON [ SILICON ]
