C8051F50x-F51x
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
SCR[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA2; SFR Page = 0x00
Bit
Name
Function
7:0
SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
SYSCLK
f
= ---------------------------------------------------------------
SCK
2 x SPI0CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
f
= -----------------------------
SCK
2 x 4 + 1
f
= 200 kHz
SCK
SFR Definition 25.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
SPI0DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA3; SFR Page = 0x00
Bit Name
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
Function
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
Rev. 1.1
261
SILICON [ SILICON ]
