C8051F50x-F51x
Table 25.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
*
Master Mode Timing (See Figure 25.8 and Figure 25.9)
SCK High Time
1 x TSYSCLK
—
—
—
—
ns
ns
ns
ns
T
T
T
T
MCKH
MCKL
MIS
SCK Low Time
1 x TSYSCLK
1 x TSYSCLK + 20
0
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
*
MIH
Slave Mode Timing (See Figure 25.10 and Figure 25.11)
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x TSYSCLK
2 x TSYSCLK
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
T
T
T
T
SE
SD
4 x TSYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x TSYSCLK
5 x TSYSCLK
5 x TSYSCLK
2 x TSYSCLK
2 x TSYSCLK
—
—
SCK Low Time
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
—
SIH
SOH
SLH
4 x TSYSCLK
8 x TSYSCLK
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x TSYSCLK
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
264
Rev. 1.1
SILICON [ SILICON ]
