C8051F50x-F51x
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
MISO
NSS (4-Wire Mode)
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
MISO
NSS (4-Wire Mode)
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1)
25.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
258
Rev. 1.1
SILICON [ SILICON ]
