C8051F50x-F51x
24.3. Configuration and Operation
UART0 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications application, or as a node on a multi-processor serial interface. To operate in a point-
to-point application, where there are only two devices on the serial bus, the MCE0 bit in SMOD0 should be
cleared to 0. For operation as part of a multi-processor communications bus, the MCE0 and XBE0 bits
should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the
TX0 pin, and received on the RX0 pin. The TX0 and RX0 pins are configured using the crossbar and the
Port I/O registers, as detailed in Section “20. Port Input/Output” on page 177.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transceiver, as shown in Figure 24.5.
TX
CP2102
PC
USB Port
USB
USB-to-UART
C8051Fxxx
RX
Bridge
OR
TX
RX
TX
RX
MCU
C8051Fxxx
Figure 24.5. Typical UART Interconnect Diagram
24.3.1. Data Transmission
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) will be set at the end of any transmission (the beginning of the stop-bit time). If
enabled, an interrupt will occur when TI0 is set.
If the extra bit function is enabled (XBE0 = 1) and the parity function is disabled (PE0 = 0), the value of the
TBX0 (SCON0.3) bit will be sent in the extra bit position. When the parity function is enabled (PE0 = 1),
hardware will generate the parity bit according to the selected parity type (selected with S0PT[1:0]), and
append it to the data field. Note: when parity is enabled, the extra bit function is not available.
24.3.2. Data Reception
Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR0 in register SCON0 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and
the RI0 flag will be set. Note: when MCE0 = 1, RI0 will only be set if the extra bit was equal to 1. Data can
be read from the receive FIFO by reading the SBUF0 register. The SBUF0 register represents the oldest
byte in the FIFO. After SBUF0 is read, the next byte in the FIFO is immediately loaded into SBUF0, and
space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI0
is set.RI0 can only be cleared to 0 by software when there is no more information in the FIFO. The recom-
mended procedure to empty the FIFO contents is:
1. Clear RI0 to 0.
2. Read SBUF0.
3. Check RI0, and repeat starting at step 1 if RI0 is set to 1.
246
Rev. 1.1
SILICON [ SILICON ]
